A Compact Design of a Two-stage Piecewise Linear ADC Used for Sensor Linearity Improvement

Abstract

This paper presents a compact two-stage piecewise linear analog-to-digital converter (ADC) that enhances sensor linearity while featuring a reduced design complexity. Unlike a traditional two-stage piecewise linear ADC, the proposed architecture achieves the same resolution with fewer components by using a single flash ADC for both conversion stages and by adding a comparator at the start of each conversion stage. The flash ADC has a resolution of (n/2−1) bits, where n is the total resolution of the two-stage piecewise linear ADC. This compact architecture enables efficient and simultaneous linearization and digitization of sensor output while significantly reducing energy consumption and implementation costs. Numerical results confirm the compactness and cost-effectiveness of the proposed design, showing up to a 75 % reduction in comparator count and up to a 25 % reduction in resistor count compared to the traditional design of the two-stage piecewise linear ADC with the same total resolution. These significant savings make the proposed two-stage piecewise linear ADC design well-suited for applications with strict energy and space constraints.