Parametric Faults Detection in Analog Circuits using Variable Ranking-based Feature Selection Method and Optimized SVM Model

Abstract

This work proposes an optimized support vector model and a variable ranking-based test node selection approach for identifying parametric faults in analog circuits using a fault dictionary. Test node selection is essential for fault dictionary-based fault detection to reduce the dimensionality and test process complexity. To determine an appropriate set of test nodes, a feature selection technique based on variable ranking is used, as it is computationally efficient and involves sorting and score estimation. In the proposed method, test nodes are ranked using a score function based on data variability, where the nodes with the highest data variability are assigned the highest rank. This ranking ensures that the most informative test nodes are prioritized for fault detection. An optimized support vector model is used for fault diagnosis to improve classification accuracy. The results show the effectiveness of this approach. The performance of the proposed method is validated by measuring the fault detection accuracy on benchmark circuits.